FDF Seminar: The FPGA design for the L0 trigger of the RICH detector of the NA62 Experiment at CERN SPS (M. Barbanera)

Tuesday 26 Nov 2024, 16:00 → 17:00 Europe/Zurich

Davide Cieri (Max Planck Society (DE)), Francesco Gonnella (University of Birmingham (GB)), Rui Zou (Cornell University (US))

The NA62 experiment focuses on precisely measure the extremely rare kaon decay with multiple detectors, producing an abundant data flux. A hardware trigger system reduces this amount, comprising the RICH L0: five FPGAs generate clusters of hits close in time associated with the same Cherenkov circle. Three principles were paramount for the design: module reuse, FPGA occupancy, and clock frequency maximization. The architecture's core consists of 16 independent rows of four clustering cells: each cell uses its first input as a time reference and aggregates the following hits in a specified time window. A distributor allocates hits from a 25 ns bunch to each row while a collector receives the clusters and sorts them to 100 ps.
A specific data format allowed the reuse of clustering, mergers, and calculators modules. Besides the architecture, I will present the expedients that ensure combinatorial path minimization, resource preservation, and maximum throughput robustness.

16:00 → 16:10 Introduction

Speakers: Davide Cieri (Max Planck Society (DE)), Dr Rui Zou (Cornell University (US))

FDF_Seminar_November24.pdf

16:10 → 16:40 The FPGA design for the L0 trigger of the RICH detector of the NA62 Experiment at CERN SPS

Speaker: Mattia Barbanera (Universita e INFN, Perugia (IT))

202411 FDF Seminar.pdf

16:40 → 17:00 Q&A and discussion

Speaker: Dr Francesco Gonnella (University of Birmingham (GB))