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09:00
NeuraLUT-Assemble: Hardware-aware Assembling of Sub-Neural Networks for Efficient LUT Inference
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Marta Andronic
(Imperial College London)
Oliver Cassidy
(Imperial College London)
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09:00
hls4ml
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Benjamin Ramhorst
(ETH Zurich)
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09:00
Part 1: Agile Hardware Design for AI: A Hands-On Tutorial with SODA and Bambu
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Giovanni Gozzi
(Politecnico di Milano)
Michele Fiorito
(Politecnico di Milano)
Vito Giovanni Castellana
(Pacific Northwest National Laboratory)
Antonino Tumeo
(Pacific Northwest National Laboratory)
Fabrizio Ferrandi
(Politecnico di Milano)
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11:00
Super Neural Architecture Codesign Package (SNAC-Pack)
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Dmitri Demler
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11:00
Designing and Deploying Low-Latency Neural Networks on FPGAs with HGQ and da4ml
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Chang Sun
(California Institute of Technology (US))
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11:00
Part 2: Agile Hardware Design for AI: A Hands-On Tutorial with SODA and Bambu
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Giovanni Gozzi
(Politecnico di Milano)
Michele Fiorito
(Politecnico di Milano)
Vito Giovanni Castellana
(Pacific Northwest National Laboratory)
Antonino Tumeo
(Pacific Northwest National Laboratory)
Fabrizio Ferrandi
(Politecnico di Milano)
Nicolo Ghielmetti
(CERN)
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11:00
Coyote v2: Open-source Abstractions and Infrastructure for FPGAs
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Benjamin Ramhorst
(ETH Zurich)