Speaker
Description
The OCTOPUS (Optimized CMOS Technology for Precision in Ultra-thin Silicon) project, part of the DRD3 collaboration, aims to simulate, develop, and characterise fine-pitch monolithic sensors using the 65 nm TPSCo CMOS process. The project targets a spatial resolution of 3 µm, a temporal resolution below 5 ns, a material budget of 50 µm of silicon equivalent, and an average power consumption below 50 mW/cm² to meet the requirements of vertex detectors in future lepton colliders experiments.
OCTOPUS places significant emphasis on the extensive simulation effort, which aims to improve sensor layouts. This includes simulations of standard process sensor designs with different readout options and moderate pitches of ~20 µm, and n-gap designs with smaller pitch. Building on past studies of n-blanket and n-gap designs, current research also explores ways to improve deep n-implant geometry.
The sensor simulation strategy combines TCAD static simulations and high-statistics Monte Carlo simulations, both of which are essential for guiding sensor design and performance optimization.
Based on simulation results and previous studies of sensors produced with the same technology, the expected hit rate in the vertex detector of future lepton colliders was assessed, showing that they are in line with OCTOPUS performance goals.
This contribution presents simulation results for sensors with various pixel pitch configurations, including both standard and n-gap layouts.
| Type of presentation (in-person/online) | in-person presentation |
|---|---|
| Type of presentation (I. scientific results or II. project proposal) | I. Presentation on scientific results |