Introduction

• Mathieu Saccani (CERN)

Room: 774/1-079

HSE/RP

• Clyde Laforge (CERN)

Room: 774/1-079 Reliability is crucial for safety-critical systems like CROME. In this presentation, I’ll walk through the different methods our team uses to keep our gateware code as bug-free as possible. We’ll cover directed tests, Python/HDL co-simulation, formal verification, and full HW/SW co-simulation—discussing their strengths, weaknesses, and what works best for a small teams such as ours at CERN.

TE/MPE

• Antoine Colinet (CERN)

Room: 774/1-079 Development flow and tools on an example project Focus on Standard IEC62566

SY/EPC

• Valerio Nappi
• Adrian Byszuk (CERN)

Room: 774/1-079 Development flow and tools on an example project Focus on the methodology used in EPC (example project)

SY/BI

• Konstantinos Blantos

Room: 774/1-079 Gateware verification flow for the BLM LHC processing FPGA Focus on tools (CI, linter, cheby, VUNIT, HDLmake, script for requirement, documentation…)

Discussion Room: 774/1-079