Speaker
Description
We present a fast-timing-oriented digital readout architecture for TOF-PET detector modules based on the HRFlexToT front-end ASIC and a calibrated multi-channel FPGA Time-to-Digital Converter (TDC). Following the earlier UTOFPET detector developments, the firmware and timing back-end have been redesigned from scratch with specific emphasis on timing digitization robustness, channel-level validation, and scalability. The proposed TDC is based on a tapped-delay-line architecture with Nutt interpolation and offline calibration through histogram-derived bin-width estimation and characteristic-curve reconstruction. Measurements on Cyclone 10 devices show that placement-aware implementation is essential to control non-uniform bins induced by clock-region boundaries, reducing ultra-bins from about 200–300 ps to 30–120 ps. In channel-level tests on Cyclone 10, a 256-tap, 64-bin configuration with 2 ns clock period yields an LSB of 35.1 ps, an ultra-bin of 110.5 ps, and 40.2 ps rms timing precision, while resource estimates indicate compatibility with 64-channel integration on the target device. In parallel, the timestamp aggregation and USB3 readout chain have been validated up to 1 Gbps, corresponding to 32 Msps total throughput or about 500 ksps per channel over 64 channels. These results establish a validated digital timing platform for scalable fast-timing PET instrumentation.
| Track | FTMI |
|---|---|
| Presentation type | Poster |