Tanawin:
- feedback from hls4ml projects presentation
- updates on Partial Reconfig project
George
- Generic updates
Noemi
- Generic updates
Speakers:
Georgios Flengas
(CERN),
Nicolo Ghielmetti
(CERN),
Noemi D'Abbondanza
(Sapienza Universita e INFN, Roma I (IT)),
Sioni Paris Summers
(CERN),
Tanawin Devaveja
- Tanawin
- DFX4ML with skip connections
- hls4ml multigraph with skip connections not supported, and VitisAccelerator doesn't support multiple I/O
- These contributions might be a PR to hls4ml, since they are quite general
- Both handled by Tanawin, for the DFX4ML solution
- Magic Streamer RTL block provided by Tanawin, handles load/store of axi-streams in the "cache" (which is actually the Magic Streamer itself
- Feedbacks from hls4ml roundtable
- Lots of interests, Chang asked about the latency of PR and he said that it dominates the computation: Tanawin said it depends on the batch size
- George
- CGRA4ML
- Utilize both CPU and FPGA in the SoC
- Heavy tasks are on FPGAs
- Easier tasks are on CPUs
- Generates SystemVerilog RTL
- Easier to port to NanoXplore and AMD wrt HLS
- CI/CD integration available
- Support both Bare-Metal and PetaLinux
- Support Keras and QKeras
- Not sure if QONNX is supported, George will check it
- After George will take a deep look into the GitHub repo, it will be good to have a meeting with Ryan Kastner
- Ask about MADOS models to AGS tomorrow, if they are ready to be ingested from our side and more details about input/output channels
- Nicolò
- NanoXplore tools are installed, issue with license and Qt plugin
