Dimitrios Lampridis : "HDL Workflows and CI/CD for FPGAs and Firmware: the case for Evergreen""

by Dimitris Lampridis (CERN)

Thursday 30 Oct 2025, 09:00 → 10:00 Europe/Zurich

774/R-013 (CERN)

A recent trend in HDL development has been the adoption of many of the established best practices in the software world, especially from the field of Continuous Integration/Development (CI/CD). At CERN, as witnessed through the many such discussions taking place in the Electronics Forum [1], as well as from the recent introduction of the CI4FPGA [2] infrastructure from the IT department, several groups are already leveraging such techniques in their FPGA design workflows.

Evergreen [3] is the code-name used for the ongoing effort in the BE-CEM-EDL section to shorten our HDL development, deployment and maintenance times through popular CI/CD techniques. The main goals are:

* to be able to automatically build the complete project, including gateware, firmware, drivers, user-space software and documentation.

* to handle versioning, releases and deployments.

* to improve code quality and readability through static analysis.

* to provide automatic verification through simulations and tests on actual hardware with test reports and reproducible test sequences.

The aim of this talk is to:

a) provide an overview of the various tools and methods used in BE-CEM-EDL for HDL development with real project examples.

b) introduce the audience to Evergreen and the features that are already implemented.

c) trigger a first discussion regarding the prospect of opening up Evergreen to the wider CERN electronics community.

[1]: https://confluence.cern.ch/display/EF/Electronics+Forum+Home

[2]: https://engineering-software.docs.cern.ch/eda/ci4fpga/

[3]: https://gitlab.cern.ch/be-cem-edl/evergreen/gitlab-ci

20251030-CEMTM_HDL_Workflows.pdf