Speaker
Description
The INFN IGNITE project is developing technical solutions in CMOS 28-nm technology for the next generation of trackers at colliders, which require high time resolution at the pixel level (<50 ps RMS), pixel size around 50 µm, and system power density below 1-2 W/cm2, depending on the specific cooling technique adopted.
We present test results about a prototype ASIC, the Ignite64, featuring a matrix of 64x64 pixels, equipped with 1 TDC per pixel, and conceived to test prototype silicon sensors of 55 µm pitch, developed within the AIDAInnova initiative in recent years. The Ignite64 is designed according to a modular architectural concept which is being replicated in the large-area ASIC, named the IgnitER (320x256 pixels, 45 µm pitch, die size 1.6x1.4 cm2), now close to submission.
The Ignite64 implements solutions for accurate power and clock distribution, which are key to obtain high and uniform performance in timing. Different solutions for the Analog Front End have been designed and tested, to accurately characterize their response concerning performance vs power.
At 1 fC input charge and 10 µW per pixel, typical measured time resolution is around 20 ps (AFE + TDC) at 0 input capacitance, which increases to around 35 ps RMS when a 3D silicon sensor is connected (100 fF typical pixel capacitance). Value dispersion on the the distribution of resolutions per pixel is kept under control, showing around 5 ps RMS error on the full matrix. This demonstrates the success of the adopted architecture and circuital solutions for powering (localized LDO).
These and other results from the Ignite64 tests are precious indications for the design of the IgnitER. The architectural choices adopted for the IgnitER, and its expected performance, as obtained from IgnitER post-layout simulations, are also illustrated.