Speaker
Description
Hybrid pixel detectors, where the sensor and the readout electronics are fabricated independently and interconnected via bump-bonding, have become the standard technology for X-ray detection at synchrotron beamlines and FEL facilities. They enable independent optimization of sensor and readout electronics, where advanced in-pixel processing can be integrated.
Several state-of-the-art detectors for FEL applications, such as AGIPD and JUNGFRAU, leverage adaptive gain front-ends, in which different gain blocks can be enabled depending on the amount of the charge delivered by the sensor. However, these designs typically rely on architectures with shared analog-to-digital converters (ADCs), where the transmission of analog data through different regions of the chip could potentially lead to data corruption and signal integrity issues.
In this work, a proof-of-concept, 28 nm CMOS front-end that combines a dual-gain charge sensitive amplifier (CSA) architecture together with Time-over-Threshold (ToT) digitization is discussed as a compact alternative to standard ADC-based readout. While ToT conversion has been widely adopted in high-energy physics readout chips (as for RD53), its extension to X-ray science has been less explored.
The developed channel features a CSA gain switching mechanism that preserves single-photon sensitivity at low signal levels while extending the upper range to around 4000 photons at 9 keV. The CSA output is processed by a comparator, whose output pulse duration is digitized by means of an 8-bit counter running at 1 GHz, yielding a conversion window of around 250 ns (compatible with the inter-pulse spacing at most existing and planned FEL facilities). A 1-bit gain flag is stored together with the 8-bit ToT value to unambiguously identify the active gain mode. A minimum SNR of 8 has been obtained from the characterization of one sample of the front-end channel.
The design and the characterization of the front-end channel will be discussed in detail in the conference paper.