Speaker
Description
The LHCb Ring Imaging Cherenkov (RICH) sub-detectors will undergo a major upgrade of their opto-electronics chain in the next decade. The upgrade will take place in two steps and will start first with the electronics chain upgrade during the LS3 Enhancement program for RUN 4, followed by a sensor replacement for Upgrade II during RUN 5. A novel front-end ASIC, the FastRICH, was designed to fulfill the requirements of the next generation RICH fast-timing readout chains with single-photon operation regime.
The FastRICH is a collaboration effort between CERN EP-ESE department and University of Barcelona and features a radiation-hard with digital-on-top design in a 65 nm CMOS technology node. It provides 16 single-ended input channels that can be configured to allow working either in positive or negative polarity. Due to its wide input dynamic range between 50 μA to 5 mA, it allows the coupling of various single-photon sensitive sensors such as: Multi-Anode Photomultiplier Tubes (MaPMTs), Silicon Photomultipliers (SiPMs), or Micro-Channel Plate sensors (MCPs). Every channel includes two discrimination processing paths: leading-edge discriminator (LED) and constant-fraction discriminator (CFD). The LED is based on direct discrimination of the input signal with a threshold value. It allows measuring time-of-arrival (TOA) with 24.41 ps bins and time-over-threshold (TOT) bins of 390.62 ps and up to a maximum range of 100 ns. The CFD allows for time walk correction and gives only the corrected signal TOA information. Overall, the recovery time for the analog processing part is better than 10 ns. The timing information is obtained with a built-in 16-channel time-to-digital converter (TDC) with performances down to 24.41 ps bins (ultrafine mode) and per channel auto-calibration capabilities. A hardware gate is implemented to filter out the data from the TDC outputs. Within a 25 ns window, the gate can be precisely set with configurable start time in 195.32 ps steps, and up to 6.25 ns length in steps of 24.41 ps. The ASIC is compatible with the LHCb readout framework by supporting Experiment Control System (ECS) for configuration over I2C protocol and Timing and Fast Control (TFC) for synchronization. An event-driven readout protocol is used for transmitting the data and it dynamically adapts to the number of hits that may arrive in the same bunch crossing event. Data is encoded with the commercial Aurora 64b/66b protocol, and it can be sent through serializers with a configurable speed between 0.32 Gbps and 5.12 Gbps. The power consumption has been optimized for less than 16 mW/channel with the ASIC powered at 1.2 V nominal voltage. Finally, the FastRICH will be integrated in a 10 mm x 10 mm plastic molded QFN88 package.
The ASIC was submitted to the foundry for a MPW run in February 2025 and the first naked dies have been received in May 2025. In parallel, massive efforts have been put together to characterize the ASIC with a dedicated FPGA-based and in-house designed system. The lab characterization tests have been carried out with the ASIC wire-bonded to a test board and without a sensor coupled to its inputs. So far, all the blocks inside the ASIC are working as expected. The analogue blocks inside the ASIC behave according to simulations. The linearity measurements of the digital-to-analogue (DACs) periphery blocks are matching the simulation results. The ASIC embeds a built-in threshold scan functionality that allows to scan the noise levels in the channels over the ECS and without relying on the full readout path. This is done by counting the number of discriminator rising edges (LED and CFD) that are triggered by the electronic noise. The results show consistent noise σ values across all 16-channels. The output jitter of the internal Phase-Locked Loop (PLL) has been optimized to ~5.81 ps, being very close to the expectations and in response to an external reference clock with ~1.5 ps jitter. The TDC blocks proved to have very good linearity. The standard deviation of the differential non-linearity (DNL) value was measured to be below 6 ps, while the integral non-linearity (INL) was obtained to be in the range of +/- 24 ps. All the interfaces are working as expected. Tests with external triggered test pulse injection and with the full readout chain have been performed with success. The power consumption was measured to be between 11 - 13 mW/ch, being strongly dependent on the configuration and on the hit rate.
The FastRICH ASIC and its pre-production validation campaign represents a very important milestone to achieve in the timeline of the future LHCb RICH upgrade programs. More results regarding the characterization of the FastRICH in the lab will be presented at the workshop.