31 August 2026 to 4 September 2026
US/Pacific timezone

Scaling Out hls4ml for ASICs: A Surrogate Model for Neural Network Accelerator Synthesis Metrics

1 Sept 2026, 17:00
12m
QI Auditorium

QI Auditorium

Presentation Extended Abstract Contributed Talks

Speaker

Arghya Ranjan Das (Purdue University)

Description

Custom ASIC accelerators offer significant power and performance advantages for machine learning in scientific and edge computing; a driving example is superconducting qubit readout, where moving real-time classification of qubit states from room-temperature FPGAs into the cryostat requires custom ASICs on cryo-compatible technology nodes. However, obtaining accurate area and timing requires synthesis runs that can take hours per design. This not only makes exhaustive design-space exploration infeasible but also limits emerging AI-driven and agentic design flows, in which an optimization loop may need to evaluate thousands of candidate designs. A surrogate model sidesteps the synthesis bottleneck by learning to predict synthesis metrics directly from a design specification and synthesis directives, without running synthesis at all. Such models were recently introduced for hls4ml accelerators on FPGA targets, but two challenges remain: extending the approach to ASIC synthesis and generalizing predictions to architectures outside the training distribution. We address both. We present a large-scale ASIC synthesis dataset and surrogate models that predict area, latency, and throughput for dense neural network accelerators generated by hls4ml and synthesized with Siemens Catapult HLS. The dataset contains over half a million designs targeting Nangate 45nm, spanning a wide range of network depths, layer widths, bitwidths, and reuse factors, on which we train and compare Transformer and Graph Neural Network surrogates. On held-out designs, our best model achieves $R^2 = 0.9997$ for latency and $R^2 = 0.9991$ for area; throughput is computed exactly rather than learned. These results, however, reflect interpolation within the training distribution. The second challenge surfaces under depth extrapolation: when trained on $n$-layer designs and tested on deeper $(n+m)$-layer networks, the same models degrade sharply; at $n=2$ and $m=1$, for example, latency $R^2$ falls to $0.634$ and area $R^2$ to $0.789$. The degradation suggests that, although the models interpolate accurately, they do not fully capture the structural overheads that each additional layer introduces, including control logic, pipeline coordination, and intermediate buffering. Integrating a sum-decomposition strategy into the model restores near-interpolation accuracy, with latency $R^2$ of $0.9954$ and area $R^2$ of $0.9797$. Finally, we demonstrate cross-node transfer: a model pre-trained with Nangate 45nm fine-tunes to the room-temperature GlobalFoundries 22FDX PDK using only $10\%$ of the pre-training data volume (${\approx}50{,}000$ designs), reaching latency $R^2$ of $0.9984$ and area $R^2$ to $0.9393$. This establishes open-library pre-training as a scalable data strategy for nodes whose PDKs are not yet ready for large synthesis campaigns, such as the cryogenic extension of 22FDX targeted for in-cryostat readout, and reduces the cost of evaluating a candidate design from hours of synthesis to milliseconds of inference, fast enough to embed in automated design-space exploration and agentic optimization loops.

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Authors

Aaron Young (Oak Ridge National Laboratory) Angelos Ioannou (Lawrence Berkeley National Laboratory) Arghya Ranjan Das (Purdue University) Ben Hawks (Fermi National Accelerator Lab) David Burnette (Siemens EDA) Davide Braga (Fermi National Accelerator Lab) Farah Fahim (Fermilab) Giuseppe Di Guglielmo (Fermi National Accelerator Lab) Hershel Weiner (The University of Texas) Jason Weitz (University of California, San Diego) Javier Mauricio Duarte (Univ. of California San Diego (US)) Kyle Woodworth (Fermilab) Mia Liu (Purdue University) Nhan Tran (Fermi National Accelerator Lab)

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