Fast Machine Learning for Science Conference 2026

STRIDE: An Automated Design Space Exploration Workflow for Generating AI Training Datasets from Hierarchical Mathematical Kernels

Not scheduled

12m

Presentation Contributed Talks

Speakers

Angelos Ioannou (Lawrence Berkeley National Laboratory) Giuseppe Di Guglielmo (Fermi National Accelerator Laboratory) John Shalf (Lawrence Berkeley National Laboratory)

Description

Developing efficient hardware accelerators for mathematical kernels remains a labor-intensive process, traditionally requiring deep expertise in low-level hardware description languages and extensive manual optimization. While high-level synthesis tools and domain-specific hardware generators have improved productivity, the space of achievable designs for any given kernel is vast, and navigating it systematically remains an open challenge. This gap motivates a new approach: systematically enumerating the design space and using the resulting data as training material for AI-driven hardware design tools.

We introduce STRIDE (Synthesis Tool for Rapid Integrated Design Engineering), an automated workflow for generating large-scale hardware implementation datasets targeting mathematically structured FPGA kernels. STRIDE is built around a hierarchical decomposition methodology in which complex mathematical algorithms, including matrix-matrix multiplication (GEMM), streaming Fourier transforms (FFT), and QR factorization, are expressed as compositions of reusable primitive building blocks such as arrays of multiply-accumulate units, butterfly networks, and permutation stages. This structure reflects the true computational dependencies of each algorithm, enabling implementation parameters to be varied independently at each level and yielding a combinatorially rich, structurally coherent design space.

STRIDE drives this design space through an automated synthesis and evaluation loop built on the AMD Vivado toolchain. For each configuration, the workflow generates a complete RTL design wrapping the unit under test, executes synthesis, reuses synthesized netlists across all matching implementation strategies, and parses the resulting reports to extract resource utilization and achievable frequency via a worst-negative-slack heuristic. The flow furthermore spans various FPGA targets across multiple AMD families and device sizes, while synthesis-to-implementation strategy pairs form an additional parameter axis capturing how Vivado's built-in optimization strategies interact with kernel structure and device characteristics. STRIDE deploys on supercomputer clusters: on NERSC's Perlmutter, multiple Vivado runs execute in parallel within each node of Slurm job arrays. To handle HPC scheduler time limits, STRIDE implements checkpoint-aware execution; when a job is killed at timeout, it automatically resumes from the last valid state, ensuring no completed work is wasted. A post-processing step aggregates results into a structured CSV ready for ML training, and generates diagnostics on synthesis and implementation success rates with structured failure annotations (e.g., routing failure, device capacity exceeded).

Crucially, the dataset produced by STRIDE is not a flat collection of design points. Because each implementation is generated from a known hierarchical composition of primitives with explicit parameter settings (streaming width, pipeline depth, unroll factors, precision, interface flavor, tool choice, target FPGA, and synthesis-implementation strategy) every data point carries rich structural metadata. STRIDE has already produced approximately 100,000 fully implemented designs across the three target algorithms and their constituent primitives, with data collection ongoing. This scale and richness make the dataset directly suitable for ML models targeting hardware design tasks, including resource and timing prediction, design space pruning, and hardware-aware neural architecture search. By releasing this dataset alongside the STRIDE workflow, we aim to lower the barrier for the fast ML community to engage with FPGA accelerator design as both a target application domain and a source of structured, reproducible benchmarks.