Speaker
Description
Recent advances in machine learning and microelectronics are enabling efficient real-time, on-chip data processing under stringent latency, power, and bandwidth constraints. Compact machine-learning models implemented directly in hardware can replace or augment fixed logic for intelligent feature extraction, classification, and denoising at the detector front-end. These capabilities are broadly relevant to next-generation detector readout in high-energy physics, as well as adaptive control, accelerator diagnostics, and other low-latency autonomous systems.
We present an end-to-end design and implementation of tiny real-time machine learning for FPGA-based edge signal processing, targeting highly latency- and resource-constrained detector readout systems. The neural network architecture is co-designed with the hardware implementation to satisfy strict resource and timing requirements while preserving physics performance. We further demonstrate how open-source toolchains, combined with agentic workflows, can streamline the full development path from model design and hardware-aware optimization to RTL generation, validation, and deployment.
This workflow accelerates cross-disciplinary co-design by reducing the engineering overhead required to integrate machine-learning kernels into real-time hardware systems. It enables rapid iteration, and provides a scalable path toward deploying intelligent front-end processing in future detector and embedded systems.