Fast Machine Learning for Science Conference 2026

SparsePixels++: Scalable Sparse Convolution on FPGAs

Not scheduled

20m

Poster Reception & Poster Session

Speaker

Ho-Fung Tsoi (University of Pennsylvania)

Description

Modern particle physics experiments often impose strict latency constraints (microseconds or below) on the edge electronics to extract quality signals from noisy raw data in real time. For 2D image data where signals are spatially sparse, standard CNNs are inefficient because latency and resources scale directly with image size, as every input pixel is densely convolved, including the vast empty regions. In this work, we introduce SparsePixels++, an upgraded framework for accelerating sparse convolution on FPGAs that adds flexible control over parallelization, making it possible to scale to larger image and model sizes than our previous approach (arXiv:2512.06208). It trains sparse CNNs with high-granularity quantization and a trainable cap on the active pixels computed, which sets the dataflow size in hardware, so that hardware cost is co-optimized with model performance for FPGA deployment via hls4ml. Evaluated on the neutrino LArTPC dataset from MicroBooNE and the muon chamber dataset from LHC experiments at CERN, SparsePixels++ achieves significant speedups with controlled resource usage.