Speakers
Description
Boosted decision trees (BDTs) are widely used in latency-critical applications, but efficient FPGA deployment remains challenging. Existing designs often rely on uniform or manually tuned fixed-point formats, which can introduce unnecessary hardware cost or accuracy loss. This work presents FQTree, a framework combining fine-grained quantization-aware training with automatic hardware generation for BDTs. It introduces a hardware-oriented leaf-value quantization scheme that uses a global quantization step together with a tree-wise shift, enabling compact non-negative integer leaf representations, controlled clipping/pruning, and bias folding to reduce datapath cost. FQTree further applies this quantization during boosting so that later trees adapt to the errors of the already-quantized ensemble, and lowers the trained model to low-latency FPGA hardware through a compiler-based flow. Results on JSC, MNIST, and NID show that FQTree reduces LUT usage by 30–50% compared to the state-of-the-art BDT designs while matching or improving accuracy.
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