Speaker
Description
On-detector data reduction has become a primary constraint for next-generation monolithic active pixel sensors (MAPS) operated in continuous readout, which are used in particle physics to realize high-resolution, low-material-budget tracking and vertexing detectors. As pixel pitches decrease and hit rates increase, the bandwidth, power, and material-budget cost of this data transport is becoming a dominant constraint on detector design. On-chip inference provides a means to reduce the data volume at the source while preserving the information required for track reconstruction. The performance of this approach depends on the neural-network architecture and its implementation cost in silicon, which must be quantified through full hardware implementation. We present a systematic comparison of compact architectures for embedded on-chip inference, with the objective of characterizing the design space rather than optimizing a single configuration. Several architecture families are evaluated as a function of network size and quantization precision. For this exploratory study, each design point is implemented in a standard 28 nm CMOS process to obtain hardware-grounded metrics, including area, power, latency, and on-chip memory, and to determine how these scale with architectural and quantization choices. This process provides a cost-effective basis for comparing the embedded-AI architectures, capturing the relative trade-offs and scaling behavior that transfer to a MAPS-compatible CMOS imaging technology required for full sensor integration. The networks are trained on single-layer detector-response simulations calibrated against test-beam data and evaluated on a set of low-level tasks, including noise rejection, hit clustering, and the reconstruction of basic track observables. By comparing architectures on a common basis, this study quantifies their relative trade-offs and identifies the families compatible with MAPS-class tracking-layer constraints. The results provide guidance for selecting embedded-AI building blocks for future low-power, low-material-budget, AI-boosted MAPS sensors for next-generation tracking and vertexing detectors in particle and nuclear physics.