This presentation investigates why different C++ data layouts can produce different performance even when they represent the same data and execute the same benchmark kernel. Focusing on a Random Invariant Mass workload, the work uses hardware performance counters and structural layout analysis to study whether the observed performance differences can be explained by cache and memory-hierarchy behavior. The results show that slower layouts do not mainly execute more instructions, but instead incur higher cycle costs and more cache-related activity, especially when useful fields are grouped with large unused data.