hdl-registers: The Smart Way to Build AXI-Lite IP Cores

by Bernhard Wandl

Tuesday 24 Nov 2026, 16:00 → 17:00 Europe/Zurich

Developing IP cores for FPGAs requires efficient and error-free implementation of register interfaces, especially when using standard protocols like AXI-Lite. The open-source project hdl-registers provides a powerful solution to simplify and automate this process.

This talk demonstrates how to quickly and consistently develop an AXI-Lite-compatible IP core using hdl-registers. Instead of manually implementing register definitions in HDL and maintaining a separate software interface, hdl-registers allows a single declarative register description. From this, HDL implementation, software headers, and documentation are automatically generated, reducing effort, avoiding inconsistencies, and improving code quality.

By the end, participants will understand how to leverage hdl-registers to streamline AXI-Lite IP core development and accelerate their projects.