CERN Computing Seminar

SEJITS: embedded specializers to turn patterns-based designs into optimized parallel code

by Dr Timothy Mattson (Intel Corp.)

IT Auditorium (CERN)

IT Auditorium



All software should be parallel software. This is natural result of the transition to a many core world. For a small fraction of the world's programmers (efficiency programmers), this is not a problem. They enjoy mapping algorithms onto the details of a particular system and are well served by low level languages and OpenMP, MPI, or OpenCL. Most programmers, however, are "domain specialists" who write code. They are too busy working in their domain of choice (such as physics) to master the intricacies of each computer they use. How do we make these programmers productive without giving up performance?

We have been working with a team at UC Berkeley's ParLab to address this problem. The key is a clear software architecture expressed in terms of design patterns that exposes the concurrency in a problem. The resulting code is written using a patterns-based framework within a high level, productivity language (such as Python). Then a separate system is used by a small group of efficiency programmers to translate that code into a highly optimized program. This software transformation system is called SEJITS: Selective Embedded Just In Time Specializers.

In this talk, I will describe the overall vision behind this work, including the patterns that sit at its core. Most of the talk, however, will focus on SEJITS. We will explore how SEJITS works and show its use for a few applications. We'll close with some thoughts on where this technology might evolve and hopefully move into the mainstream of parallel computing.

About the speaker

Tim Mattson is a parallel programmer (Ph.D. Chemistry, UCSC, 1985). Tim has been with Intel since 1993 where he has worked with brilliant people on great projects such as:

  • the first TFLOP computer (ASCI Red),
  • the OpenMP API for shared memory programming,
  • the OpenCL programming language for heterogeneous platforms,
  • Intel's first TFLOP chip (the 80 core research chip), and
  • Intel's 48 core, SCC research processor.

Tim has published extensively including the books Patterns for Parallel Programming (with B. Sanders and B. Massingill, Addison Wesley, 2004), An Introduction to Concurrency in Programming Languages (with M. Sottile and C. Rasmussen, CRC Press, 2009), and the OpenCL Programming Guide (with A Munshi, B. Gaster, J. Fung, and D. Ginsburg, Addison Wesley, 2011).

Organised by: Sverre Jarp and Miguel Angel Marquina
Computing Seminars /IT Department

more information
Video in CDS