CERN Computing Seminar

Debugging and Optimizing Applications for Multi core MPP Architectures

by Gordon Cook (Allinea Software)

Europe/Zurich
IT Auditorium (CERN)

IT Auditorium

CERN

Description

As two, four and potentially eight-core processors become the norm, the de facto HPC architecture is tending towards large clusters of modest 8-16 core shared-memory servers, potentially with co-processing devices (e.g.. GPGPUs, FPGAs, Clearspeed). Programming these machines optimally presents a number of challenges, and applications that use mixed programming models are now becoming commonplace.

In this presentation we will discuss the challenges facing today's HPC application developers, and the need for simple software tools that can address mixed programming models (MPI and OpenMP/threads). We will present new multicore features of Allinea's Distributed Debugging Tool (DDT) and Optimisation and Profiling Tool (OPT), and discuss our aims to provide a consolidated, scalable, yet intuitive framework for HPC developers.

We will also discuss the competitive software tools market and compare arch rival products with both DDT and OPT and show where the Allinea software tools bring greatest benefit.

This will be followed by a demo of both DDT and OPT and a Q&A session at the end.

more information
Slides
Organized by

Sverre Jarp