CERN Computing Seminar

Directions in parallel processor architecture, and GPUs too

by Olivier Giroux (NVIDIA)

Friday, 27 June 2014 from to (Europe/Zurich)
at CERN ( 31-3-004 - IT Amphitheatre )

Modern computing is power-limited in every domain of computing. Performance increments extracted from instruction-level parallelism (ILP) are no longer power-efficient; they haven't been for some time. Thread-level parallelism (TLP) is a more easily exploited form of parallelism, at the expense of programmer effort to expose it in the program. In this talk, I will introduce you to disparate topics in parallel processor architecture that will impact programming models (and you) in both the near and far future.

About the speaker

Olivier is a senior GPU (SM) architect at NVIDIA and an active participant in the concurrency working group of the ISO C++ committee. He has also worked on very large diesel engines as a mechanical engineer, and taught at McGill University (Canada) as a faculty instructor.

more information
Video in CDS
Organised by
Axel Naumann/PH Department and Miguel Angel Marquina
Computing Seminars /IT Department