Xilinx Seminar

by Mr Carlo Reinhart (Xilinx Field Application Engineer), Mr Markus Hennersperger (Silica Field Application Engineer Xilinx)

Wednesday 28 May 2008, 09:00 → 17:00 Europe/Zurich

40-S2-B01 (CERN)

This seminar will present the latest news and updates involving Xilinx FPGAs and the design software. 9.00h Registration and Introduction 9.30 – 10.30h Advanced Timing Closure Techniques - Coding for performance with the right timing constraints - How PlanAhead accelerates your work 10.30 – 11.30h DSP Design Methodologies - Design challenges implementing DSP algorithms in Xilinx FPGAs; - How AccelDSP and System Generator support you 11.30 – 12.30h Multi-Gigabit Transceiver, PCI Express and 1Gbps Ethernet - How to implement PCIe and 1Gbps Ethernet in Xilinx FPGAs 12.30 – 13.30h Lunch 13.30 – 14.30h Memory Interfaces - How to use the Memory Interface Generator (MIG) 14.30 – 15.30h Embedded Processing - Implementing Embedded Systems in Xilinx FPGAs - How the Embedded Development Kit structures your design process 15.30 – 16.30h Virtex-5 FXT - Embedded processing with serial connectivity 16.30 – 17.00h Questions and Answers