Description
This poster describes the planned feasibility studies to use Intel Xeon/Phi CPUs, the new concept of a Xeon-FPGA based accelerate compute platform and the Omni-Path network in the foreseen Event Filter Farm of the LHCb Upgrade in 2018, in which the whole detector readout chain will be modified to make a detector readout of 40 MHz possible.
The Intel Xeon/Phi is a coprocessor architecture, which uses a Many Integrated Core architecture and is optimized for highly parallelized tasks. The new Knights Landing version is interesting not only for the greater speed-up, due to a high number of computational cores +50, especially it is better integration with the Intel Omni-Path network, which is also considered to be used as network technology in the future Event Filter Farm.
The concept platform of a Xeon-FPGA based computing accelerator uses a CPU linked via a high speed link to a high performance FPGA, on which an accelerator is implemented. The FPGA has cache-coherent memory access to the main memory of the server and can collaborate with the CPU. At the beginning the performance of a Muon Trigger using a normal CPU will be compared with the performance of the Muon Trigger using the accelerator platform.
Speakers
Christian Faerber
(CERN)
Karel Ha
(Charles University (CZ))
