Hewlett-Packard is preparing a Vector Math Library for the IA-64 architecture to appear later this year. During 1998-99 the library was prototyped and validated in collaboration with CERN. The library deploys several new algorithms and exploits the 82-bit floating-point registers as well as the software pipelining capability of the new Intel architecture. Together these features offer exceptionally good accuracy, very high speed and full versatility across the whole range of arguments. The speaker will discuss all these features in turn in order to demonstrate the value of this new mathematical library.