OTHER SEMINARS - RD49 Seminar on Cryogenic electronics:<br>What's on Today: <br>Operation of CMOS integrated electronics at cryogenic temperatures: ch

by Shahyar Saramad (CERN and University of Teheran)

Friday 19 Oct 2001, 14:30 → 15:30 Europe/Zurich

13-2-002 (CERN)

It is well-known that CMOS integrated circuits can reasonably operate at cryogenic temperatures. However it exists almost no well established experience in precise parameter modeling and adapted analog circuit design technique for this operating temperature range. Results of the MOS parameter extraction of a quarter micron CMOS technology done from 20K to 300K with the compact EKV model will be presented, and limitation of the current model will be discussed. An example of a fast low noise preamplifier ASIC designed for the NA60 experiment optimized for cryogenic application will be presented.

Organiser(s): Pierre Jarron / EP Division