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Technical Training Seminar
The Summit Design VisualElite 4.0 Release
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Europe/Zurich
593--011 (CERN)
593--011
CERN
Description
Summit Design is an important EDA digital hardware design tool supplier, and the industry leader in the emerging Electronic System Level design domain. Its VisualElite program has been used at CERN for several years. This seminar will include the highlights of the program's latest release.
It will be illustrated how Summit Design products can provide a high-level C/C++ and SystemC functional modelling design and verification environment, enabling engineers to analyse system concepts before the implementation stage. The seminar will show how mixed SystemC and HDL simulation can be done, along with solutions for hardware/software development.
• HDL new features: Connectivity Table Editor. Xemacs full integration. New NCsim simulation integrations. Assertions with PLS/Sugar/IBM_FoCs integration.
• SystemC "Embracing a System Level Language". The role for a system level language.
• VisualElite 4.0 system level design: Mixed SystemC / HDL multi-level entry and verification. Hardware/Software co-development solutions. VisualElite embedded software core based designs: ARM, PowerPC405 (Xilinx), others.
• New partnerships. New integrations.
This seminar will be of interest to digital hardware designers, and also to people implicated in system level design. This could include all projects that would benefit from fast and accurate mixed hardware/software simulation.
Language: English
Free seminar, no registration
Organiser(s): Serge Brobecker / IT-PS / 78693 Serge.Brobecker@cern.ch
Davide Vitè / HR-PMD / 75141 Davide.Vite@cern.ch
Please read the full information on the Technical Training Seminars pages http://www.cern.ch/TechnicalTraining/special/TTseminars.asp or contact the organisers.
It will be illustrated how Summit Design products can provide a high-level C/C++ and SystemC functional modelling design and verification environment, enabling engineers to analyse system concepts before the implementation stage. The seminar will show how mixed SystemC and HDL simulation can be done, along with solutions for hardware/software development.
• HDL new features: Connectivity Table Editor. Xemacs full integration. New NCsim simulation integrations. Assertions with PLS/Sugar/IBM_FoCs integration.
• SystemC "Embracing a System Level Language". The role for a system level language.
• VisualElite 4.0 system level design: Mixed SystemC / HDL multi-level entry and verification. Hardware/Software co-development solutions. VisualElite embedded software core based designs: ARM, PowerPC405 (Xilinx), others.
• New partnerships. New integrations.
This seminar will be of interest to digital hardware designers, and also to people implicated in system level design. This could include all projects that would benefit from fast and accurate mixed hardware/software simulation.
Language: English
Free seminar, no registration
Organiser(s): Serge Brobecker / IT-PS / 78693 Serge.Brobecker@cern.ch
Davide Vitè / HR-PMD / 75141 Davide.Vite@cern.ch
Please read the full information on the Technical Training Seminars pages http://www.cern.ch/TechnicalTraining/special/TTseminars.asp or contact the organisers.
