Xilinx Design-Resources for High Speed Designs

by Mr Kellermann (Xilinx)

Tuesday 8 Mar 2005, 09:30 → 12:00 Europe/Zurich

IT Auditorium (CERN)

This Technical seminar will focus on Xilinx Design-Resources for High Speed Designs. As interfaces run at higher speeds, with faster edge rates and shrinking bit periods, ensuring Signal Integrity and Power Integrity becomes increasingly critical to a successful system implementation. Virtex-4 FPGAs incorporate advanced technology to deliver significant system design benefits. These advanced design techniques will help you to improve signal and power integrity, minimize package and PCB inductance, reduce noise and reduce jitter.

Agenda

1. PCB
   * Potential problems with designs above 3 Gbs
   * Solutions
   * Xilinx Design-Resources for Designs @ 10 Gbs
   
2. Power
   * Power Consumption
   * Decoupling
   * Xilinx Design-Resources to Design a Power Distribution System
   
3. Virtex-4 architecture
   * IO functionality (Serdes, DDR interface, bit deskew and ChipSync
   
4. Demo and measurements
   
5. Questions and Answers.