Cadence day at CERN

by Gilles Corsand , Jean-Yves Pateyron (Cadence France)

Tuesday 10 May 2005, 09:00 → 17:30 Europe/Zurich

IT Auditorium (CERN)

The day will cover some important topics and tools that help electronic designers to produce successful working designs in the shortest time.

There will be two main sessions. They will be:


Session 1: Cadence Silicon-Package-Board Co-Design tools and methodologies.
Producing logically correct and verified code is insufficient to produce a working design. PCB layout considerations are essential for production design reliability to try and avoid expensive and time-consuming re-working.
The Cadence high-speed design flow allows control of the final PCB layout to be carried through from the initial drawing to production. Layout constraints discovered at the design phase can be entered into a common electrical management environment that can directly guide the auto/interactive PCB routing.
In addition, this session will describe tools specifically aimed at multi-gigahertz communication channels (including multi-GHz SerDes FPGAs ), and high-speed printed circuit board power-plane noise problems.

Session 2: Cadence Incisive platform for simulation and verification of logic designs.
NC-SIM is a well known digital simulator that has been used for many years at CERN. Cadence has now intoduced the Incisive platform that provides an integrated design environment natively supporting Verilog, VHDL and analog/mixed-signal simulations.
It also offers SystemC and formal verification capabilities along with Acceleration-on-Demand, transaction-level support, HDL analysis (linting), coverage analysis and test generation possibilities.
This session will describe the main features of the Incisive platform with emphasis on verification techniques.

FULL AGENDA

09:00, SESSION 1: Cadence Silicon-Package-Board Co-Design tools and methodologies
Gilles Corsand / Cadence

• Welcome
  
• Constraint Manager Introduction
  
• Allegro Design Entry HDL SI 610 (Front End schematic environment + constraint developments through electrical simulation)
  
• Presentation
  
• Design-in Kits introduction
  
• Allegro Design Entry HDL SI 610 Demo
  
• coffee
  
• Allegro PCB SI 630 (simulation solution for multi-gigahertz serial-transmission: PCI EXpress, etc...)
  
• Presentation
  
• Allegro PCB SI 630 Demo
  
• Allegro PCB Power Integrity Option 610 (PCB power-distribution analysis)
  
• Presentation
  
• Q&A and follow-ups
  

12:30 LUNCH


14:00 SESSION 2: Cadence Incisive platform for simulation and verification of circuit designs
Jean-Yves Pateyron / Cadence

• Incisive Introduction : what is Incisive (vs. NCSim)?
  
• The Verification Challenge: what is Verification?
  
• Flow concepts: The Functional Virtual Prototype
  
• Flow proposal: The Advanced Verification Flow
  
• The Incisive Verification Platform
  
• Overview of the different components
  
• (Optional) Technology Update on the Debugging environment (SimVision)
  
• The AMS extension for the Simulation of analog designs
  
• Overview of AMS-designer flow
  
• Movie-demo (10')
  
• coffee
  
• Verification Methodology
  
• The Assertion-Based Methodology
  
• Overview
  
• Introduction to a property language (e.g. PSL/Sugar)
  
• ABV within the Incisive Platform
  
• From simulation to formal analysis
  
• Verification Metrics
  
• The Comprehensive Coverage solution
  
• Coverage concepts and types
  
• Coverage within the Incisive Platform
  
• Q&A and follow-ups

17:30 END


Organiser(s): John Evans, Serge Brobecker, Jean-Michel Sainson / IT-DES - Engineering Tools Service