Euromedim 2006 :1st European Conference on Molecular Imaging Technology

A Front-End Readout Mixed Chip for High Efficiency Small Animal PET imaging.

10 May 2006, 14:00

1h

Palais du Pharo, Marseille

poster • Electronics, read out, data acquisition Poster session : detection modules and electronics

Speaker

Mr Nicolas OLLIVIER-HENRY (Institut Pluridisciplinaire Hubert-Curien, UMR 7178 CNRS/ULP)

Description

Today, the main challenge of Positron Emission Tomography (PET) systems dedicated to small animal imaging is to obtain a high efficiency event data collection with a good sensibility and a high accurate localization. If the focus is only on the PET characteristics, an accurate spatial resolution depends as well on the design of detector as its electronics readout system. In this paper, we present a new design of such readout system with full custom sub-micrometer CMOS implementation. The chip consists of two main blocks in which the energy information and temporal nanosecond resolution data can be obtained. In our AMISSA PET device design, a matrix of LYSO crystals has to be read at each end by a 64 channels multi-anode photomultiplier tube. Then a specific readout electronic has been developed at IPHC. The architecture of this readout for the energy information detection is composed of a low noise preamplifier, a CR-RC shaper and an analog memory. In order to obtain the required dynamic range from 0.3 to 650 photoelectrons with good linearity, a current mode approach has been chosen for preamplifier. To detect only the useful signal with a temporal resolution of one nanosecond and to eliminate the interference due to the afterglow generated by the crystal, a double in time comparing system with a low threshold (0.3 photoelectron) has been implemented. It gives the time reference of arrival signal coming from the detector. In order to obtain the time coincidence with a temporal resolution of one nanosecond, a Time-to-Digital Converter (TDC) based on a Delay- Locked-Loop (DLL) has been designed. The chip is fabricated with AMS 0.35 m process. The ASIC architecture and some simulation results will be presented in the paper.