Speaker
Mr
Jung Yeol Yeom
(University of Tokyo)
Description
Individual readout of detectors in Positron Emission Tomography (PET) scanners
give a better spatial resolution and counting rate over light sharing or charge
division schemes. However, this will greatly increase the number of readout
channels and is difficult to implement with bulky conventional front-end
electronics especially with small detector systems like animal PET. To achieve
individual readout of large numbers of channels, the use of compact front-end
electronics, especially when space is restricted, are required. Application
Specific Integrated Circuit (ASIC), being highly integrated, power efficient and
reliable, is a promising alternative to conventional front-end electronics while
allowing simple integration of analog and digital components.
A high resolution avalanche photodiode (APD) based animal PET with depth-of-
interaction (DOI) information has been proposed. Each detector module consists of
two or more crystals with different decay times, for example GSO doped with
different Ce concentrations, that are stacked as in a phoswich detector and each
crystal of the lowest layer is coupled to each pixel of a multi-element APD for
individual readout. An improved 9-channel (including 1 test channel) Waveform
Sampling Front-End (WSFE) ASIC based on a previous design has been fabricated using
Rohm 0.35u CMOS technology for readout of signals from each pixel at an early
stage. Each channel of the ASIC comprises of a preamplifier, a variable gain
amplifier (VGA), a fast ADC and digital encoder to digitize the incoming signal
which can then be used to obtain DOI information by pulse shape discrimination
(PSD). Each component was analyzed using the test channel. The preamplifier is
optimized for low capacitance APD and is based on the telescopic-cascode topology.
It has a gain of 1.4/pF and the linearity is less than 0.5% over -0.35 pC to 1.1
pC. The rise time is 20ns and the minimum Equivalent Noise Charge (ENC) is 480 e- +
20 e-/pF rms at a shaping time of 0.25 us. A single-stage VGA instead of the two-
stage VGA as in the previous chip was adopted to eliminate offset errors as
observed before. The gain can be varied from about 5 to 16 by two external digital
inputs. The ADC is identical to that of the previous chip. It is a folding ADC
which works at least up a rate of 100 Msamples/s. The DNL and INL were calculated
to be 1.1 LSB and 1.4 LSB respectively. To test for the whole channel, two pulses
with rise times of 50 ns and 100 ns were fed into the preamplifier. It was shown
that the rise times of the two digitized and amplified signals could be
distinguished from each other. Finally, the power consumption of the whole chip was
measured to be about 1 W when working at 100 MHz.
GSO crystals with Ce dopant concentration of 0.5, 1.0 and 1.5 mol% will be
coupled to a Hamamatsu APD to examine the DOI capabilities using this WSFE chip.
The digitized signals from the WSFE chip can be fed into a FPGA to obtain DOI
information by comparing the rise times.
Author
Mr
Jung Yeol Yeom
(University of Tokyo)
Co-authors
Dr
Hideo Murayama
(National Institute of Radiological Sciences, Japan)
Prof.
Hiroyuki Takahashi
(University of Tokyo)
Prof.
Masaharu Nakazawa
(University of Tokyo)
