CRU Weekly meeting (07 December 2016)
Present: Shuaib, Jubin, Sanjoy, mazsi, Erno, Tivadar
Secretary: Erno(12), PiPPo(9), Shuaib(1), mazsi(7)
Actions:
- automated test scripts should be created - needed by the hw testing, also answers EDR comments.
Report on Actions:
- 1st CRU FW was released (v20161130).
- CRU EDR reiview happend on Dec 1, went reasonably well, another follow up will be scheduled.
- Altera devkit in Kolkata - The extra power connector is still not connected. Only less power hungry designs possible (no PCIe endpoint).
1. 10G PON
- preparing for test measurements with trigger group.
- looking into the integration of Arria 10 PON ONU release from central electronics team.
- Erno looked into the firmware running on the KC705 CTP emulator from trigger group: many xilinx specific code, but located "business logic". will ask trigger group if we should wait for final (kintex ultrascale) version.
2. GBT
- Erno started creating unified test scripts (supporting both JTAG & PCIe based register access). written in TCL. current version was tested with JTAG (works as before) & C lib based memory mapped PCIe BAR access. will look into using pascal's command line tools now.
- GBT was tested with quartus 16.1, seems to work.
- Tivadar: test fw/scripts for testing 48 GBT link is needed (HW production + card stress testing).
- we should follow up TPC's code rewrite efforts (GBT, SCA), see if we can reuse it.
- should also check GBT FPGA 4.0.1, and 240 MHz implementation (not urgent).
3. DCS
- i2c was tested with quartus 16.1, on both Altera A10 cards (in CERN, in india). register access worked on both, problem with i2c access seems to be solved (as expected, based on jean-pierre cachemice's email). full external PLL reprogramming was only tested on card in india.
- i2c should be tested in the integrated design, too.
- EC/IC block (integrated into the 1st FW release) has timing errors.
- sanjoy will migrate the matlab based i2c config generator (for external PLL) to c.
4. PCIe
- pippo & sanjoy will continue with the PCIe idle time measurements.
- we should start looking into using both PCIe endpoints on the pcie40.
5. Integration
- we should move to quartus 16.1, integrated design released (v20161206).
AOB
- jubin has some time left for measurements before leaving. should discuss today the planned measurement (kintex ultrascale (?) with PON OLT design from eduardo + A10 PON ONU design from eduardo + GBT + VLDB).
Travels/Vacations
- Shuaib: will leave on 3 December, not available next week.
- Jubin: will leave on 12 December.
- Mazsi: will work from Wigner/Budapest on 2016 w50 & 2017 w2, on vacation between them.
There are minutes attached to this event.
Show them.
