CERN Computing Seminar

FPGA Compute Acceleration for High-Throughput Data Processing in High-Energy Physics Experiments

by Christian Faerber (CERN)

Europe/Zurich
31-3-004 - IT Amphitheatre (CERN)

31-3-004 - IT Amphitheatre

CERN

105
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Description

The upgrades of the four large experiments of the LHC at CERN in the coming years will result in a huge increase of data bandwidth for each experiment which needs to be processed very efficiently. For example the LHCb experiment will upgrade its detector 2019/2020 to a 'triggerless' readout scheme, where all of the readout electronics and several sub-detector parts will be replaced. The new readout electronics will be able to readout the detector at 40MHz. This increases the data bandwidth from the detector down to the event filter farm to 40TBit/s, which must be processed to select the interesting proton-proton collisions for later storage. The architecture of such a computing farm, which can process this amount of data as efficiently as possible, is a challenging task and several compute accelerator technologies are being considered.   

In the high performance computing sector more and more FPGA compute accelerators are being used to improve the compute performance and reduce the power consumption (e.g. in the Microsoft Catapult project, Bing search engine and Amazon EC2 F1 Instances). Therefore different types of FPGA compute accelerators are being developed by different companies with compute performances of up to 10 TFlops. Many of these accelerators are already available on the market or will become available very soon, like the Intel Xeon+FPGAs. In addition, simpler programming models like OpenCL are becoming more popular for application development, which allows easier programming and maintenance of the FPGA firmware in a high-level language. FPGAs are especially interesting in the metric of performance per Joule, which, for larger data-centers, is very important when considering that power and cooling costs drive the total operational budget.

In this talk different performance studies with HEP algorithms will be shown and discussed, which were performed for the LHCb upgrade in the High-Throughput-Compute Collaboration with Intel. Different types of FPGA compute accelerators are compared, including studies of their programming model with OpenCL and Verilog. In addition, the performance per Joule will be discussed. The results show that the new Intel Xeon+FPGA platforms, which are built in general for high performance computing, are very interesting for the High Energy Physics community. 

At the end of the talk the outlook is given for the near future development of the FPGA compute acceleration.

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