The White Rabbit Project (J. Serrano) and FPGA Mezzanine Cards for CERN's Accelerator Control System (J. Serrano)

Thursday 1 Oct 2009, 09:00 → 10:00 Europe/Zurich

864/1-C02 - indisponible a partir du 24/04/2017 (CERN)

White Rabbit: The General Machine Timing system was designed more than 20 years ago. Since then, a series of hardware generations have complied with its specified physical layer, imposing a bandwidth limit of 500 kb/s and one-way traffic flowing only from the master to the slaves. For the next hardware generation, the BE-CO-HT section proposes to use a new physical layer that will overcome these two limitations while allowing a gradual (and optional) upgrade of existing infrastructure. The presentation will not deal at all with deployment considerations - for which it is too early - but will focus exclusively on the technological choices of the White Rabbit Project. FPGA Mezzanine Cards/Open Hardware: In the frame of the ACCOR project, the BE-CO-HT section must provide a standard kit of hardware modules, along with appropriate low level software support. The platforms to be covered include now PCI and PCIe in addition to the already-supported VMEbus. The presentation will focus on the technological choices to fulfill this mandate and discuss in addition the Open Hardware design paradigm and its advantages for increasing design quality and driving down maintenance costs.