CRU Weekly Meeting

Wednesday 30 May 2018, 11:00 → 12:00 Europe/Zurich

CERN

Present

Olivier, Tuan, Tivadar, Sanjoy, PiPPo

 

PCIe

 

• CVP protocol under investigation with Sanjoy, as we see no progress on the flash topic
• To work, we have to enable identical IP for both endpoints and use only one in practice

 

TTC uplink and clocking scheme (Tuan)

 

• global240 adjustement to be done
• txclk was deisgned with fPLL
• Some cleaning, about to propose for merge
• Olivier will wait that and then add documentation for TTC and adress table right after

 

The GLIB card was fixed, packet from CRU are seen

GBT

 

• Work in progress to bring this in the gbt_link and make it transparent to users
• Need to test MID features
  • Next week, MID come at CERN, loopback will be then tested

 

Integration

 

• Timing fixes included in develop, rebase all design

 

PRR

PRR most complex points:

• (1) Ressource point, not possible to answer, cannot happen in the coming weeks.
  • We want to test the integration of the user logic, and release as soon as posisble, perfect release does not exist
  • Difficult to answer yet to ressource reduction : "detailled plan" -> contact TPC?
• (2) Rebase firmware with the latest of develop to prepare for merge
• (3) was done with 120m cable
  • Add a 8 bit counter. issue #49 : error counter before correction. Not urgent!
• (4) Tivadar propose that Erno take develop and fill up a user logic with a tunable toggle rate
  • Try a single and worst scenairo and see if more is needed
• (5) Scripts for reading minipod temperatures are avalaible
  • Add more I2C masters, see https://gitlab.cern.ch/alice-cru/pcoresng-cru/issues/48
• (6) Yes with DMA
• (7)
• (8) About to be done, thanks to fixes by Tuan
• (9 to 11) Result for jitter measurement. Measurement on the die are impossible, and measure on the PCB is not representative anyway.
• (12) Specific heating cycle and dedicated analysis
• (13) Cannot be done for PRR
• (14) ?
• (15) Yes by contract
• (16) use of scenario 2
• (17) Cannot be done for PRR
• (18) The warping was measured by fabrication company, it should be OK. Is it really an issue for reliability? Does it exist on bare PCB already or after assembly?
  • First notify Jean-Pierre and then ask of the company (see point 14)
• (19) We are aware, documentation is integrated in the git and we will provide support
• (20) Lower speed, we could parallelize. See with Guido (Phd Heidelberg)
  • PiPPo will contact him, and try to get numbers
• (21) It is always possible, it is matter of money. Pippo asked TPC for numbers. For 2 CRU per FLP : 36 Gb/s with cluster finder 60Gb/s without. If we stay below 100Gb/s the Ethernet is already available on the mother board, if we go to twice of that we need an extra Ethernet card and cabling.

 

 

ABSENCES

 

• Pippo, in travel from june 8 to june 24 (8 to 13 in meeting and should be reachable)