present: Roland, Giovanna, Eric, Milo, Frank, Junbin, Kai, Brett
EHN1 integration:
- after BR implementation: continued focus on throughput optimisation
- now three versions:
- FDR version by Jörn: i/o vectors => 5.7 Gb/s max
- optimisation using Infiniband support: Infiniband w/ single buffer: 20 Gb/s (single full-mode link) -- but unable to use this from within felixcore
- publishing through fdaq (using Infiniband): 7 Gb/s, uses ~ 70% of one core (the reduction w.r.t. the above 20 Gb/s is thought to be solvable)
- next step: attempt to use in felixcore
- felixcore: extraction of chunks uses a lot of CPU
- NB: new WIB f/w available, also needs to be tested
BNL WIB-FELIX testing:
- (see slides)
- now testing with one WIB, 4 FEMBs (256 channels); different pedestal settings for induction/collection wires
- see different noise for different gains (seems to scale with gain)
- using fdaq/fcheck, see data errors for data sent by WIB (e.g missing data) but not when using internal emulation
- also observe some issues by data sent from felixcore to subscriber (testBW) when using FLX712
DUNE R&D plans:
- (see slides; these were shown by Brett also the preceding day, in the DUNE DAQ PI meeting)
- two FELIX oriented R&D tasks were suggested:
- demonstrate feasibility of using FELIX to receive dual-phase data from uTCA crates
- DP aims to use UDP (data are sent by commercial modules mounted on uTCA crates. It does not seem straightforward to change this
Giovanna's suggestion: BNL is best equipped to study if alternatively, FELIX can adapt to UDP input data
- additional item (but less FELIX specific): DP trigger primitive finding
- discussion: it would be good to see who could contribute what to these studies
- [ note: the above is in addition to already existing SP tasks ]
Next meeting: tentatively on April 18
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