EP-IT Data Science Seminars

HLS4ML: deploying deep learning on FPGAs for L1 trigger and Data Acquisition

Name: HLS4ML: deploying deep learning on FPGAs for L1 trigger and Data Acquisition
Start: 2018-04-25T11:00:00+02:00
End: 2018-04-25T12:00:00+02:00
Location: CERN

by Jennifer Ngadiuba (CERN)

Wednesday 25 Apr 2018, 11:00 → 12:00 Europe/Zurich

500/1-001 - Main Auditorium (CERN)

500/1-001 - Main Auditorium

CERN

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Description

Machine learning is becoming ubiquitous across HEP. There is great potential to improve trigger and DAQ performances with it. However, the exploration of such techniques within the field in low latency/power FPGAs has just begun. We present HLS4ML, a user-friendly software, based on High-Level Synthesis (HLS), designed to deploy network architectures on FPGAs. As a case study, we use HLS4ML for boosted-jet tagging with deep networks at the LHC. We show how neural networks can be made fit the resources available on modern FPGAs, thanks to network pruning and quantization. We map out resource usage and latency versus network architectures, to identify the typical problem complexity that HLS4ML could deal with. We discuss possible applications in current and future HEP experiments.

Organised by

M. Girone, M. Elsing, L. Moneta, M. Pierini.......... Refreshments will be served at 10h30

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HLS4ML: deploying deep learning on FPGAs for L1 trigger and Data Acquisition

by Jennifer Ngadiuba (CERN)

500/1-001 - Main Auditorium

CERN