EP-ESE Electronics Seminars

The PCIe40 board and the importance of efficient production tests

by Jean-Pierre Cachemiche (Centre National de la Recherche Scientifique (FR))

Europe/Zurich
13/2-005 (CERN)

13/2-005

CERN

90
Show room on map
Description

LHCb has chosen a trigger-less architecture which means that all data from the subdetectors are routed up to the farms. The hardware trigger is replaced by a software filtering of data on the fly. In such a system the interface between front-ends and computer farms is assured by a powerful acquisition board in PCI Express form factor able to process up to 500 Gbits/s: the PCIe40 card.
This talk presents the main features of this card and the way it has been tested.
Just before launching the production intensive tests have been run on the card. They allowed to detect a critical issue causing the supension of the production in September 2018.
We  will report the long investigation that was necessary to solve the problem. The talk will point out tricky points to care about when designing cards with most recent FPGAs, the limits of operation and some inefficiencies in current design tools.