Speaker
Description
We present the experimental results obtained with the FAST2 ASIC. It is a picosecond resolution front-end electronics to read out Ultra-Fast Silicon detectors (UFSD). It has been optimized to achieve a combined time resolution below 45 ps. The ASIC implements the standard 110 nm CMOS technology and 20 readout channels. The ASIC power rail is at +1.2 V, achieving a power consumption of 2.4 mW/ch. Each FAST2 readout channel presents an amplifier, a comparator stage, and an LVDS driver as the output stage.
The experimental tests include a Large Scanning-TCT with a 1060 nm wavelength laser diode. Here, the FAST2 ASIC, couples to a UFDS with a capacitance of 3.4 pF, achieves a timing jitter lower than 12 ps at 15 fC of input charge. The successive experimental tests measure the full temporal resolution of the UFSD-ASIC system using a beta telescope. The Sr90 beta source on the UFSD adds a new uncertainty source due to the MIP non-uniform energy depositions. The Landau noise adds an uncertainty of 30 ps, achieving a combined time resolution around 40-45 ps for a bias voltage equal to 200 V.
The future prototype to readout UFSD will implement a structure of 32 readout channels. Each channel occupies an area of 500x500 𝜇𝑚2. 2/3 of the space is for the analog circuits, such as an amplifier, discriminator, and 4-blocks of time to digital converter (TDC). The remaining area will be for the digital circuit for pixel control logic and data transmission. The readout channel can operate at the maximum system clock frequency of 320 MHz, achieving a time resolution, for the TDC, around 25-50 ps LSB, and a conversion rate around 700-350 ns depending on the TDC configuration. Then, considering there is no additional noise contribution in the TDC, its uncertainty contribution to the combined time resolution is around (25 ps)/√12.
The new IC prototype can operate in 3 modes. Primarily the Time of Arrival (ToA) operation, which provides the time of the particle arrival with a time resolution of 25 ps, and a conversion rate of 750 ns. However, the ToA operation only occupies 1 TDC, then we can work with the rest of TDC simultaneously, reducing the conversion rate by 4 (175 ns). Secondly, the Time of Threshold (ToT) operation measures the time of an event amplitude is over a specific threshold. The ToT operation requires 2 TDCs to compute the leading and trailing edge. Then, the conversion rate is reduced by 2 in this case (350 ns). The last operation mode is the ToA and amplitude. Here, the readout channel output measures the ToA and the event amplitude, with an operation rate equal to 350 ns.
The new FAST2 version will be submitted to the foundry at the end of the year, and we might test it in the early spring.
