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EP-ESE Electronics Seminars
In-sensor processing for high-speed low-power 2D and 3D imaging
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Europe/Zurich
4/3-006 - TH Conference Room (CERN)
Description
Architectural adaptation to the nature of the stimulus results in improved processing speed and reduced power consumption. Image data have a high degree of parallellism that can be exploited by using distributed processing elements and memory. The research group on Smart Imagers and Vision Chips at IMSE has built a number of CMOS image sensors that incorporate parallel image processing capabilities right at the sensor plane. In-sensor processing can be employed to speed up feature extraction, to reduce data bottlenecks and increase the frame rate, and to eliminate redundant information at early stages of vision. Working examples of these functionalities will be provided.
