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TWEPP 2020 User Group Meetings

21–24 Sept 2020
Europe/Zurich timezone

Contribution List

33 out of 33 displayed
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  1. 1. Project Overview: brief recap
    Francois Vasey (CERN)
    21/09/2020, 14:00
  2. 21. LpGBT
    Paulo Rodrigues Simoes Moreira (CERN), Pedro Vicente Leitao (CERN), Szymon Kulis (CERN)
    21/09/2020, 14:15
    • Status Report
    • Q&A
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  3. 2. VTRx+ front-end module
    Jan Troska (CERN)
    21/09/2020, 15:00
    • Status Report
    • Q&A
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  4. 3. Passive fiber plant
    Iacopo Toccafondo (CERN)
    21/09/2020, 15:45
    • Status Report
    • Q&A
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  5. 12. CERN-B Firefly module
    Francois Vasey (CERN)
    21/09/2020, 16:30
    • Q&A
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  6. 13. AOB
    Francois Vasey (CERN)
    21/09/2020, 16:45
  7. 14. Welcome
    Kostas Kloukinas (CERN)
    22/09/2020, 14:00
  8. 15. ASIC support & Foundry Services News
    Alessandro Caratelli (CERN, EPFL)
    22/09/2020, 14:10
  9. 16. CHIPS: CERN-HEP IC design Platform and Services
    Xavi Llopart Cudie (CERN)
    22/09/2020, 14:30
  10. 17. EP R&D WP: CMOS Technologies for Future Experiments
    Kostas Kloukinas (CERN)
    22/09/2020, 14:50
  11. 33. 28nm CMOS Mixed Signal Design Kit
    Ms Alessandra Fioriti (CERN)
    22/09/2020, 15:10
  12. 18. EUROPRACTICE EDA Tools for the HEP Community
    Manager, Europractice Design Tools
    22/09/2020, 15:40
  13. 19. Semiconductor process selection from ESD perspective: FinFET, SOI or CMOS?
    Mr Benjamin Van Camp, CTO SOFICS (SOFICS solutions for ICs)
    22/09/2020, 16:10

    Many fabless companies struggle with the selection of their next process platform: FinFET or thin film SOI or in CMOS?
    Though on-chip protection against Electrostatic discharge (ESD) should not determine the choice of technology, it can impact design choices and ultimately cost of the product. For efficient ESD protection, 2 elements are important: the ESD strategy, and the vulnerability of...

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  14. 20. Open Discussion
    22/09/2020, 16:40
  15. 4. Introduction
    Ken Wyllie (CERN), Salvatore Danzeca (CERN)
    23/09/2020, 14:00
  16. 11. FPGA On-board Power Management
    Jean-Pierre Cachemiche (Centre National de la Recherche Scientifique (FR))
    23/09/2020, 14:15
  17. 5. FPGA testing methodologies
    Luca Sterpone (Politecnico di Torino)
    23/09/2020, 14:45
  18. 6. Alice ITS FPGA radiation qualification
    Matteo Lupi (CERN / Johann-Wolfgang-Goethe Univ. (DE))
    23/09/2020, 15:20
  19. 7. NanoExplore Rad-Hard commercial FPGA
    Rudy Ferraro (CERN)
    23/09/2020, 15:45
  20. 8. Radiation-tolerant Multi-gigabit Serial Links Based on FPGAs
    Raffaele Giordano
    23/09/2020, 16:10
  21. 9. Rad-Tol RISC-V Soft Core
    Mattia Rizzi (CERN)
    23/09/2020, 16:35
  22. 22. Introduction
    Hucheng Chen (Brookhaven National Laboratory (US)), Magnus Hansen (CERN)
    24/09/2020, 14:00
  23. 28. BPOL DCDC converter family development and production status
    Giacomo Ripamonti (CERN)
    24/09/2020, 14:10
  24. 32. CMS HGCal LDO development status
    Alessandro Marchioro (CERN)
    24/09/2020, 14:35
  25. 29. Power Supply procurement progress
    Vincent Bobillier (CERN)
    24/09/2020, 14:55
  26. 26. Serial power design and test results for ATLAS Pixel detector
    Matthias Hamer (University of Bonn (DE))
    24/09/2020, 15:10
  27. 27. Serial power design and test results for CMS Inner Tracker
    Stella Orfanelli (CERN)
    24/09/2020, 15:35
  28. 25. Development of radiation tolerant 48V-11V DC/DC converter for the ATLAS ITk Strip detector
    Wladyslaw Dabrowski (AGH University of Science and Technology (PL))
    24/09/2020, 16:10
  29. 30. CMS Outer Tracker power system requirements, design, and procurement
    Simone Paoletti (Universita e INFN, Firenze (IT))
    24/09/2020, 16:35
  30. 24. ATLAS Tile LVPS development
    Seyedali Moayedi (University of Texas at Arlington (US))
    24/09/2020, 17:00
  31. 31. CMS common LVPS requirements, design, and procurement
    Krzysztof Stachon (ETH Zurich (CH))
    24/09/2020, 17:25
  32. 23. ATLAS LAr LVPS development
  33. 10. Polarfire Radiation testing