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Kostas Kloukinas (CERN)22/09/2020, 14:00
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Alessandro Caratelli (CERN, EPFL)22/09/2020, 14:10
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Xavi Llopart Cudie (CERN)22/09/2020, 14:30
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Kostas Kloukinas (CERN)22/09/2020, 14:50
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Ms Alessandra Fioriti (CERN)22/09/2020, 15:10
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Manager, Europractice Design Tools22/09/2020, 15:40
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Mr Benjamin Van Camp, CTO SOFICS (SOFICS solutions for ICs)22/09/2020, 16:10
Many fabless companies struggle with the selection of their next process platform: FinFET or thin film SOI or in CMOS?
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Though on-chip protection against Electrostatic discharge (ESD) should not determine the choice of technology, it can impact design choices and ultimately cost of the product. For efficient ESD protection, 2 elements are important: the ESD strategy, and the vulnerability of... -
22/09/2020, 16:40
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