hls4ml: Ultra low-latency deep neural network inference on FPGAs
This is a workshop tutorial from the UZH ML Workshop 
This tutorial is given by Thea Aarrestad and Sioni Summers (CERN).
With edge computing, real-time inference of deep neural networks (DNNs) on custom hardware has become increasingly relevant. Smartphone companies are incorporating Artificial Intelligence (AI) chips in their design for on-device inference to improve user experience and tighten data security, and the autonomous vehicle industry is turning to application-specific integrated circuits (ASICs) to keep the latency low. While the typical acceptable latency for real-time inference in applications like those above is O(1) ms, other applications require sub-microsecond inference. For instance, high-frequency trading machine learning (ML) algorithms are running on field-programmable gate arrays (FPGAs), highly accurate devices, to make decisions within nanoseconds. At the extreme inference spectrum end of both the low-latency (as in high-frequency trading) and limited-area (as in smartphone applications) is the processing of data from proton-proton collisions at the Large Hadron Collider (LHC) at CERN. Here, latencies of O(1) microsecond is required and resources are strictly limited. In this tutorial you will get familiar with the hls4ml library. This library converts pre-trained Machine Learning models into FPGA firmware, targeting extreme low-latency inference in order to stay within the strict constraints imposed by the CERN particle detectors. You will learn techinques for model compression, including how to reduce the footprint of your model using state-of-the art techniques such as model pruning and quantization through quantization aware training. Finally, you will learn how to synthesize your model for implementation on chip. Familiarity with Machine Learnining using Python and Keras is beneficial for participating in this tutorial, but not required.