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Christos Zamantzas (CERN)04/12/2020, 08:45
Overview of the system and its purpose
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William Vigano' (CERN)04/12/2020, 08:50
Systems deployed from L4 to TT10
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Eva Calvo Giraldo (CERN)04/12/2020, 09:00
FPGA control of the analogue circuit and its verification
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Mr Mathieu Saccani (CERN)04/12/2020, 09:10
Measurements, Settings, HW Interlocks
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David Medina Godoy (CERN)04/12/2020, 09:25
SW interlocks, BLMSYNC, UCAP/NXCALS, OP applications, ALARMS, RBAC/MCS
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David Medina Godoy (CERN), Mathieu Saccani (CERN)04/12/2020, 09:40
Completed checks and future plans
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