55 - 65Gs/s ADC's and DAC's in CMOS technology

by Mr Ian Dedic (Fujitsu semiconductor)

Tuesday 12 Apr 2011, 10:30 → 11:30 Europe/Zurich

Salle Andersson (CERN)

This talk describes how the world’s fastest ADCs and DACs are realised in standard CMOS processes, how they can be integrated with DSPs with processing power of tens of TeraOPS, what the performance limits are both now and in the future, and how they might be applied to ultrafast signal acquisition and generation.

EVO details EVO_Booking__CERN_PH-ESE_Seminar_April_12.txt

EVO pointer http://evo.caltech.edu/evoNext/koala.jnlp?meeting=MtM8Ma2i2aDsD99B9DDs9t

Slides ADC_DAC_CERN.pdf