Speaker
Dr
Annie Xiang
(Southern Methodist University)
Description
Bit error rate (BER) is a principle measure of data transmission link performance. With the integration of high-speed SERDES inside an FPGA, the embedded solution provides a cheaper alternative to dedicated table top equipment and offers the flexibility of test customization and data analysis. This paper presents a BER tester implementation in the Altera Stratix GX/GT signal integrity development kits. Architecture of the tester is described. Lab test results and field test data analysis are discussed.
The Stratix II GX tester operates up to 6.5 Gbps and the Stratix IV GT tester operates up to 10Gbps, both in 4 duplex channels. The tester deploys a pseudo random bit sequence (PRBS) generator and detector, a transceiver controller, an error FIFO logger and also includes a computer interface for data acquisition and user access. The tester’s functionality is validated and performance is characterized in an optical transmission link setup. BER vs. receiver sensitivity is measured to emulate stressed conditions. The Stratix II GX tester is also used in a proton test on custom serializer chips. Both bit flip and bit shift type of errors are recorded and analyzed.
Author
Dr
Annie Xiang
(Southern Methodist University)
Co-author
Dr
Chonghan Liu
(Southern Methodist University)
