Speaker
Valerio Re
(INFN-Pavia and University of Bergamo)
Description
The SuperB project was approved in December 2010 and foresees the construction of a high luminosity (> 10^36 cm^-2 s^-1) asymmetric e+e- collider in an Italian site. In the SuperB detector, the Silicon Vertex Tracker (SVT) is based on the BaBar vertex detector layout with an additional innermost layer (Layer0) close to the interaction point, with a radius of about 1.5 cm. This Layer0 has to provide high position resolution (10-15 um in both coordinates), low material budget (< 1% X0), and tolerance to a high background rate (several tens of MHz/cm^2). The baseline design of the SuperB SVT presently adopts the technically conservative solution of using short strip detectors (striplets) in the Layer0. However, the stringent experimental requirements stimulate an R&D program on low-mass pixel sensors, which is exploring CMOS MAPS technology as well as 3D integration. The ambitious goal is to build a monolithic device with similar electronic functionalities as in hybrid pixel readout chips, such as pixel-level sparsification and time stamping.
This paper presents the status of the R&D activity that the VIPIX collaboration is carrying out to achieve this goal. The effort is presently focused on the design of two different devices. The first one is a deep N-well active pixel sensor based on the interconnection of two layers fabricated in the same 130 nm CMOS technology. The second one is aimed at the ultimate goal of fabricating a 3D device based on heterogeneous technologies, i.e. a high resistivity sensor layer interconnected to a 2-tier CMOS readout integrated circuit. Both devices include a high performance readout architecture which is able to handle a very large data flow. The paper reviews the technical details concerning how these two different designs may fit the requirements of the SuperB SVT Layer0; the present status of VIPIX developments using 3D integration is also discussed.
Author
Valerio Re
(INFN-Pavia and University of Bergamo)
