Conveners
Front-end Electronics
- Hans-Günther Moser (Max-Planck-Institut)
- Zheng Wang (Institute of High Energy Physics, Chinese Academy of Sciences)
Front-end Electronics
- J.P. Walder (LBNL)
Front-end Electronics
- Yasuo Arai (High Energy Accelerator Research Organization (KEK))
Front-end Electronics
- Valerio Re (INFN)
- gustavo cancelo (Fermilab)
Front-end Electronics
- Carl Grace (Lawrence Berkeley National Laboratory)
Dr
Lea Michaela Caminada
(LBNL)
09/06/2011, 16:00
Front-end Electronics
Oral Presentation
We cover development of readout integrated circuits for hybrid pixel particle physics detectors. We compare the 250nm feature size chips in the presently operating ATLAS and CMS experiments with the current state of the art in 130nm feature size represented by the FE-I4 chip that will be used to add a new beam pipe layer for the ATLAS experiment in 2013 and the upgrade options of the CMS pixel...
Valerio Re
(INFN-Pavia and University of Bergamo)
09/06/2011, 16:30
Front-end Electronics
Oral Presentation
The SuperB project was approved in December 2010 and foresees the construction of a high luminosity (> 10^36 cm^-2 s^-1) asymmetric e+e- collider in an Italian site. In the SuperB detector, the Silicon Vertex Tracker (SVT) is based on the BaBar vertex detector layout with an additional innermost layer (Layer0) close to the interaction point, with a radius of about 1.5 cm. This Layer0 has to...
Michael Cooney
(University of Hawaii)
09/06/2011, 17:00
Front-end Electronics
Oral Presentation
The next generation of vertexing detectors in collider experiments will require order of magnitude increases in readout speed and increased background rates. The CAP12 continues the evolution of a number of binary, 3T based pixel detector related technologies at the University of Hawaii to address readout speed, density requirements, and background rate issues. The CAP12 takes the HIXEL...
Dr
Gianluca Aglieri Rinella
(CERN, European Organization for Nuclear Research)
09/06/2011, 17:20
Front-end Electronics
Oral Presentation
NA62 is a new experiment at CERN Super Proton Synchrotron aiming at measuring ultra rare kaon decays.
The Gigatracker (GTK) detector shall combine performing on-beam tracking of individual particles with an excellent time resolution of 150 ps rms.
The peak flow of particles crossing the detector modules reaches 40 MHz/cm^2 for a total rate of about 1 GHz.
A hybrid silicon pixel detector is...
Bob Zheng
(Lawrence Berkeley National Lab)
09/06/2011, 17:40
Front-end Electronics
Oral Presentation
Solid-state photomultiplier (SSPM) arrays are an interesting technology for use in PET detector modules due to their low cost, high compactness, insensitivity to magnetic fields, and sub-nanosecond timing resolution. However, the large intrinsic capacitance of SSPM arrays results in RC time constants that can severely degrade the response time, which leads to a trade-off between array size and...
Dr
Carl Grace
(Lawrence Berkeley National Laboratory)
10/06/2011, 14:00
Front-end Electronics
Oral Presentation
The High-Speed Image Pre-Processor with Oversampling (HIPPO) is a prototype image sensor readout integrated circuit designed for both high performance and enhanced flexibility. HIPPO’s initial target application is the instrumentation of bufferless, column-parallel, soft x-ray Charge-Coupled Device (CCD) image sensors operating at column rates up to 10 MHz, enabling 10,000 frames-per-second...
Prof.
Gary Varner
(University of Hawaii)
10/06/2011, 14:30
Front-end Electronics
Oral Presentation
Many applications in collider detector readout and particle
astrophysics have adopted CMOS Switched Capacitor Array (SCA),
Giga-sample/second transient waveform recording as a means to provide
low-cost, highly integrated detector readout. In order to maintain
high (100's of MHz) analog bandwidth, these SCAs have typically been
limited to less than or equal to a thousand storage cells. ...
Eric Oberla
(University of Chicago),
Herve Grabas
(University of Chicago)
10/06/2011, 14:50
Front-end Electronics
Oral Presentation
We describe here the development and characterization of PSEC-3, a custom analog and digital integrated circuit designed in the IBM8RF 130 nm process, intended for fast, low-power waveform sampling. As part of the Large-Area Picosecond Photo-Detector (LAPPD) collaboration, this ASIC has been designed for the front-end transmission line readout of large area micro-channel plates (MCP), among...
Mr
Salleh Ahmad
(OMEGA/LAL/IN2P3/Université Paris Sud 11,France)
10/06/2011, 15:10
Front-end Electronics
Oral Presentation
The SPACIROC ASIC is designed for the JEM-EUSO fluorescence imaging telescope onboard of the International Space Station. Its goal is the detection of Giant Air Shower above a few 10^19 eV, developing at a distance of about 400 km, downward in the troposphere. From such distance, most of the time, the number of the photons expected in the pixels is very weak, ranging from a few units to a few...
Hucheng Chen
(Brookhaven National Laboratory (BNL)-Unknown-Unknown)
10/06/2011, 16:00
Front-end Electronics
Oral Presentation
The ATLAS experiment is one of the two general-purpose detector designed to study proton-proton collisions (14 TeV in the center of mass) produced at the Large Hadron Collider (LHC) and to explore the full physics potential of the LHC machine at CERN. The ATLAS Liquid Argon (LAr) calorimeters are high precision, high sensitivity and high granularity detectors designed to provide precision...
Dr
Kurtis Nishimura
(University of Hawaii)
10/06/2011, 16:30
Front-end Electronics
Oral Presentation
A general procedure for precision timing calibration of giga-sample/s
waveform digitizing ASICs is presented. These devices are increasingly
used in a number of high-energy physics experiments to perform
waveform sampling of front-end detector signals. Waveform digitizing
ASICs have considerable advantages over traditional TDC/ADC systems,
such as high channel density and low power...
Michael Cooney
(University of Hawaii)
10/06/2011, 16:50
Front-end Electronics
Oral Presentation
As fabrication processes continue to shrink, more and more electronics are able to be integrated on die for various physics experiments. Due to the increasing number of readout channels and required sensitivity of sensors, more dense and fast ASIC elements are required and the fabrication processes must be well understood. To this end, the University of Hawaii in collaboration with the...
Fukun Tang
(University of Chicago)
10/06/2011, 17:10
Front-end Electronics
Oral Presentation
As a detector of jets of charged and neutral particles, the ATLAS Tile Calorimeter (TileCal) is essential for measuring the energy and direction of the quarks and gluons produced in the collisions at LHC. The TileCal consists of a fine-grained steel matrix with 430,000 "tiles" of plastic scintillator dispersed in the matrix. Optical fibers from the tiles are grouped into 5,000 calorimeter...
Dr
Ken Wyllie
(CERN)
11/06/2011, 08:30
Front-end Electronics
Oral Presentation
The transmission of data from detectors in future high energy experiments will be driven by a number of requirements. In many cases, raw bandwidth is the strongest of these but other needs such as diverse functionality, compactness, low power and radiation resistance are equally important. The GigaBit-Transceiver (GBT) project has been launched to provide a solution to these problems. The aim...
Dr
Annie Xiang
(Southern Methodist University)
11/06/2011, 09:00
Front-end Electronics
Oral Presentation
The Versatile Link project is launched to develop a physical layer general purpose optical link with high bandwidth; radiation and magnetic resistance that meets the requirements of LHC upgrade experiments. This paper will present the latest results on system specifications, front-end transceiver prototypes, passive components studies and commercial back-end transceiver tests.
System...
Dr
Mike Strang
(The Ohio State University)
11/06/2011, 09:30
Front-end Electronics
Oral Presentation
The LHC (CERN), the highest energy hadron collider in the world, will be upgraded in two phases to increase the design luminosity by a factor of five. The ATLAS experiment plans to add a new pixel layer to the current pixel detector during the first phase of the upgrade. The optical data transmission will also be upgraded to handle the high data transmission speed. Two ASICs have been...
Tiankuan Liu
(Department of Physics-Southern Methodist University (SMU))
11/06/2011, 09:50
Front-end Electronics
Oral Presentation
The current front-end electronics of the ATLAS Liquid Argon calorimeters need to be upgraded to sustain the higher radiation levels and data rates expected at the upgraded LHC machine (HL-LHC), which will have 5 times more luminosity than the LHC in its ultimate configuration. This upgrade calls for an optical link system of 100 Gbps per front-end board (FEB). A high speed, low power,...
Dr
Annie Xiang
(Southern Methodist University)
11/06/2011, 10:10
Front-end Electronics
Oral Presentation
Bit error rate (BER) is a principle measure of data transmission link performance. With the integration of high-speed SERDES inside an FPGA, the embedded solution provides a cheaper alternative to dedicated table top equipment and offers the flexibility of test customization and data analysis. This paper presents a BER tester implementation in the Altera Stratix GX/GT signal integrity...
Prof.
Zheng Wang
(Institute of High Energy Physics, Chinese Academy of Sciences)
11/06/2011, 14:00
Front-end Electronics
Oral Presentation
The Daya Bay Reactor Neutrino Experiment will consist of seventeen separate detector subsystems distributed in three underground experimental halls. There will be eight PMT based anti-neutrino detectors (ADs), six water-Cherenkov detectors, and three RPC detector subsystems. Each detector will be read out using an independent VME crate. The PMT front-end electronics (FEE) board will be used...
Mr
Stéphane Callier
(OMEGA / IN2P3)
11/06/2011, 14:30
Front-end Electronics
Oral Presentation
EASIROC, standing for Extended Analogue SI-pm ReadOut Chip is a 32 channels fully analogue front end ASIC dedicated to readout SiPM detectors. This low power and highly versatile ASIC was developped from the chip SPIROC which has been designed for the Analogue Hadronic Calorimeter foreseen at the International Linear Collider.
EASIROC integrates a 4.5V range 8-bit DAC per channel for...
Dr
Tiankuan Liu
(Department of Physics-Southern Methodist University (SMU))
11/06/2011, 14:50
Front-end Electronics
Oral Presentation
A Liquid Argon Time Projection Chamber (LArTPC) has been proposed as a potential far site detector of long baseline neutrino experiment (LBNE). A cold front-end electronics scheme, in which preamplifiers, shapers, analog to digital converters, digital memories, data multiplexers, and cable drivers operates in liquid argon is under development. In this paper we present the cryogenic performance...
Dr
Peter Goettlicher
(Deutsches Elektronen Synchrotron (DESY))
11/06/2011, 15:10
Front-end Electronics
Oral Presentation
Calorimeters, like CALICE-AHCAL, aiming for particle flow algorithms need a high granularity readout in all three dimensions. That requires electronics to be integrated into the detector volume with 1000 channel/square-meter. To keep the mechanics easy and homogeneous the heat should be conducted just by the steel of the absorber layers. Therefore a heat production of 40micro-watt per channel...
