Speaker
Description
Recently, an increasing interest towards the development of novel Monolithic Active Pixel Sensors (MAPS) based on CMOS technology has spread inside the radiation detector community. The ARCADIA project aims at the development of an innovative platform for the design of MAPS exploiting a production process which is fully compatible with commercial 110nm CMOS technology. A first engineering run, including both active sensors with integrated electronics and passive test structures, has been completed in 2021. The designed sensors are fabricated on low doped n-type silicon substrates with thicknesses equal to 100 and 200 $\mu$m or, alternatively, on n-type epitaxial layers with an active thickness of 48 $\mu$m, grown on p-type silicon. The sensor is composed of a n-type collection electrode located at the pixel centre. P-type regions (pwells and deep pwells) are formed at the pixel periphery, where the front-end electronics can be hosted.
In order to select the optimal pixel layout in terms of charge collection speed, capacitance and operating voltage range, parametric simulations have been performed with a TCAD tool, focusing on the pixel layout i.e. on the dimensions of the frontside p- and n-type implants. Transient simulations on single pixel 3D domains have been used to reproduce the sensor response to an external infrared (IR) and red laser, which illuminates the devices from the backside with an unfocused light spot. Passive pixel arrays with different pixel pitches (50, 25 and 10 $\mu$m) and different pixel layouts have been tested at a probe station as well as in an optical setup employing an IR or, alternatively, a red laser.
An excellent agreement has been obtained comparing the data extracted from measurements and simulations and thus proving the reliability of the adopted device models.
We will present the obtained results from this characterization activity, focusing on the comparison between experimental and simulated characteristics and on the dynamic performance of the different pixel layouts.
