Timepix4, a pixel detector readout chip with sub-200 ps timestamp binning

by Xavi Llopart Cudie (CERN)

Friday 11 Feb 2022, 11:00 → 12:00 Europe/Zurich

Hybrid pixel detectors remain the only detector technology able to provide noise-hit-free detection with precise time tagging in high-rate environments. By using the latest available high density CMOS processes data driven readout schemes can be implemented permitting trigger free readout opening new opportunities in high energy physics and other applications. Decoupling the sensor from the readout ASIC allows novel detector morphologies and materials to be adopted. The Timepix4 ASIC contains 448 x 512 pixels compatible with an array of sensor pixels of 55 µm x 55 µm for a total active area of ~7 cm2. By using TSV technology for the IO pads, on-chip pad to pixel redistribution and ‘hiding’ all active peripheral circuitry under the pixel bump pads, we have designed a 4-side buttable chip with an effective active area > 99.5%. In Data Driven mode each detected event is registered with a Time-Over-Threshold precision of < 100 e- rms and tagged to a time bin of 195 ps. The seminar will present the new ASIC in the context of its successful predecessors, Timepix3 and VELOpix, reviewing briefly some applications. While focusing mainly on the functionality and measured results of the Timepix4 ASIC we will also outline ideas for the next generation of Timepix chips.

Recording

video1060955324.mp4

Video preview

Xavi_DS_11Feb2022.pdf