The CERN Experimental Physics Department R&D develops monolithic sensors for high energy physics and is currently investigating sub-100 nm CMOS imaging processes. In collaboration with the ALICE Inner Tracking System (ITS3) upgrade project, a Tower Partner Semiconductor Co. 65 nm ISC process is studied for the next generation sensors.
In view of the LHC Run 4, the innermost three of the seven layers of the ALICE tracking detector will be replaced with wafer-scale monolithic active pixel sensors (MAPS) produced using the stitching technique, thinned to 50 µm or below and implementing 65 nm CMOS technology in order to achieve a truly cylindrical detector with minimal material.
Among the test structures developed for the ALICE ITS3 upgrade, the Analogue Pixel Test Structure Operational Amplifier (APTS-OPAMP) is designed to allow the characterization of the charge collection and timing properties of this technology. The chip consists of a 4 by 4 square matrix of 10 um by 10 um pixels featuring small collection electrodes on a thin (~ 10 um) epitaxial layer. Each pixel is connected to a fast OPAMP placed outside the matrix to buffer the signal output of the pixel frontend to the analog output pad.
This contribution will show the performance of the presented 65 nm CMOS MAPS analog test structure, with a focus on laboratory calibration and measurements with photons and charged particle beams resulting in a time resolution of 77 ps.